1. Field of the Invention
The invention relates generally to programmable memory devices, and more particularly, to floating gate memory devices such as flash electrically erasable programmable read only memory (EEPROM) devices.
2. Description of the Related Art
Computer systems and other modern electronic equipment typically store information in electronic memory devices, each of which typically comprises an array of individual cells. One such memory device is a flash electrically erasable programmable read only memory (EEPROM). The structure and operation of an exemplary flash EEPROM device is described in U.S. Pat. No. 4,698,787, to Mukherjee et al., issued Oct. 6, 1987.
More specifically, referring to FIGS. 1 and 2, a conventional bulk silicon flash EEPROM device 100 typically includes an N.times.M array 104 of individual memory cells 110. Each cell 110, as shown in FIG. 1, typically includes: a double-diffused n-type source 112 and an n-type drain 114 formed in a p-type substrate 116; a channel 118 disposed in substrate 116 between source 112 and drain 114; and a selectively chargeable gate structure 160. Gate structure 160 suitably comprises: a floating gate 122 overlying channel 118 and overlapping the edges of drain 114 and source 112; a first layer of dielectric material, known as the tunnel dielectric 120, separating floating gate 122 from source 112, drain 114, and channel 118; a control gate 126 overlying floating gate 122; and a second layer of dielectric, known as the interpoly dielectric 124, separating floating gate 122 from control gate 126. The portion of source 112 (or drain 114) immediately underlying floating gate 122 is referred to as a tunneling region 140.
Array 104 (FIG. 2) typically includes a large number of cells 110, e.g. 1,000 or more, arranged in a series of rows and columns. Each row is driven by an associated word line (WL), comprising a conductive polysilicon layer that incorporates the control gate 126 of each cell 110 within the row. Each column is driven by an associated bit line (BL) comprising an overlying layer of metal connected to each drain 114 of the cells 110 within the column. Source 112 of each cell 110 within array 104 is coupled to a common source line CS formed by a conductive path diffused in substrate 116. Any individual cell 110 within array 104 can be individually addressed (i.e. charged and read) by operating upon one word line and one bit line.
Tunnel dielectric 120 suitably comprises a thin (e.g. approximately 100 angstroms) layer of oxide. Tunnel dielectric 120 may be formed on substrate 116 by any suitable technique, such as, for example, thermally oxidizing the surface of substrate 116 or by depositing a suitable material on substrate 116.
Floating gate 122 suitably comprises a conductive polysilicon such as polycrystalline silicon. Floating gate layer 122 may be formed by any suitable technique, such as, for example, by conventional chemical vapor deposition (CVD).
Interpoly dielectric layer 124 insulates control gate 126 from floating gate 122. Interpoly dielectric 124 suitably comprises a dielectric material, such as, e.g., an oxide-nitrate-oxide (ONO) layer, and may be formed by any suitable technique. For example, where interpoly dielectric 124 is ONO, it is suitably formed by growing a layer of oxide, depositing a layer of nitrate, followed by growing another layer of oxide.
Control gate 126, like floating gate 122, suitably comprises a layer of conductive polysilicon and may be formed on interpoly dielectric layer 124 by any suitable technique, such as, for example, by conventional chemical vapor deposition (CVD).
Control gate layer 126, interpoly dielectric layer 124, floating gate layer 122, and tunnel dielectric 120 are suitably masked and etched according to conventional methods to define the selectively chargeable stacked gate structures 160 of the respective cells.
Source 112 is typically formed by initially implanting a first n-type dopant, suitably phosphorous, to form a deeply diffused but lightly doped N well 130, establishing a graded source-channel junction. This first n-type implant is typically driven deeper into substrate 116 by subjecting substrate 116 to a thermal cycle at high temperature (e.g. 1050 degrees Fahrenheit. A shallow second n-type implant is then performed (e.g., with arsenic) to create a more heavily doped, but shallower, N +well 132 embedded within deep N well 130. This second n-type implant also forms a shallow, abrupt drain to channel junction.
EEPROM 100 suitably includes a control circuit 125 to selectively connect the source, gate and drain of an addressed cell to predetermined voltages or impedances to effect one of the operational states of the cell. Control circuit 125 is suitably connected to source 122 of each cell 110 through common source line CS; through a word line (WL) to the control gate 126 of each cell 110 in the corresponding row; and through a bit line (BL) to the drains 124 of each cell 110 in the corresponding column. The voltages presented by control circuit 125 determine the operational state of cells 110.
The various operating states of cell 110 include a charge state, a read state, and a discharge state. The voltages and impedances coupled to source 112, drain 114, and control gate 126 by control circuit 125 during each of these states depends on whether or not cell 110 is in the selected row (corresponding to word line WL) and column (corresponding to bit line BL). The connections for the various operating states of cell 110 are summarized in Table I.
TABLE I ______________________________________ V.sub.G (WL) V.sub.D (BL) V.sub.S Un- Un- Operation (CS) Selected selected Selected selected ______________________________________ Charge 0 +9 to +12 0 +5 to +7 0 Read 0 +5 0 +1 to +2 0 Discharge +12 0 High-Z (Floating) ______________________________________
The charging and discharging of floating gate 122 in prior art cell 110 typically corresponds to programming and erasing the cell, respectively. During charging, a specific memory cell 110 in a specific row and column is charged by applying the appropriate charge voltage to the selected row and column while inhibiting the charging of unselected memory cells of array 104. For example, referring again to FIG. 1, floating gate 122 of an individual cell 110 is charged through high energy electron injection, often referred to as hot electron injection. By applying the appropriate potentials to source 112, drain 114, and control gate 126, as shown in Table I, hot electrons 136A are injected from channel 118 through tunnel dielectric 120 to negatively charge floating gate 122. Charging floating gate 122 with a negative potential raises the threshold voltage of cell 110 by a predetermined amount .DELTA.V.sub.T from a first nominal value V.sub.T1 to a second nominal value V.sub.T2. As a result, a charged cell (V.sub.T &gt;V.sub.T2) conducts substantially less current during a subsequent read operation than an uncharged (or discharged) cell (V.sub.T &lt;V.sub.T1) (i.e. having no charge on floating gate 122 ).
During a read operation, a predetermined voltage V.sub.g is applied to control gate 126 of selected cell 110. If the selected cell 110 is not charged (V.sub.T &lt;V.sub.T1), the gate voltage V.sub.g typically exceeds the threshold voltage V of the cell, and cell 110 conducts a relatively high current (above a predetermined upper threshold level, e.g. 100 microamps). Conduction of such high level current is indicative of a first state, e.g., a zero or logical low. On the other hand, if the selected cell 110 is charged (V.sub.T &gt;V.sub.T2), the gate voltage V.sub.G is typically less than the threshold voltage V.sub.T2 of the cell, and the cell is non-conductive, or at least conducts less current (below a predetermined lower threshold level, e.g. 20 microamps). Conduction of such low level current is indicative of a second state, e.g., a one or logical high.
In contrast to the charging procedure, flash EEPROMs are typically bulk-discharged, so that all of cells 110 in array 104 (i.e. connected to common source line CS) are simultaneously discharged. Appropriate potentials (Table I) applied to the source 112, drain 114, and control gate 126 during the discharge state cause electron migration from floating gate 122 to source 112 or drain 114 via Fowler-Nordheim (F-N) tunneling. For example, electrons 136B stored during charging on floating gate 122 migrate through tunnel dielectric 120 to source 112 in tunneling region 140. F-N tunneling occurs simultaneously for all cells 110 within memory array 104 during the discharge state, thereby discharging entire array 104 in one "flash" or operation.
Operation of flash EEPROMs similar to that shown in FIGS. 1 and 2 from a single power supply is also known. An example is disclosed in U.S. Pat. No. 5,077,691, to Haddad et al., issued Dec. 31, 1991. Instead of providing a relatively high voltage to the source to effect discharge, a lower voltage, such as the typical power supply voltage (e.g. +5 volts), is applied to the source in conjunction with a relatively high magnitude negative voltage to the control gate. Since little current flows through the control gate, the gate voltage can be generated using on-board charge pumps. Thus, the need for a second, higher voltage (e.g. +12 volts) power supply to effect discharge is eliminated.
The array of cells employed in single supply flash EEPROMs is similar to that described in conjunction with FIGS. 1 and 2. However, in contradistinction to the earlier flash EEPROM, the charge, read and discharge operations are effected by establishing the connections to the selected and unselected cells as summarized in Table II.
TABLE II ______________________________________ V.sub.G (WL) V.sub.D (BL) V.sub.S Un- Un- Operation (CS) Selected selected Selected selected ______________________________________ Charge 0 +9 to +12 0 +5 to +7 0 Read 0 +5 0 +1 to +2 0 Discharge +.5 -13 to -7 High-Z (Floating) to +5 ______________________________________
In general, the control circuit for the single supply flash EEPROM provides the same voltages in the charge state and read state as in the multi-supply flash EEPROM 100 of FIGS. 1 and 2. Substrate 116 is grounded (V.sub.SUB =0 volts) at all times. However, in the single supply EEPROM, discharge of floating gate 122 is effected by applying a negative voltage, preferably a relatively high magnitude negative voltage (e.g., -13 volts to -7 volts), to control gate 126. Source 112 is suitably coupled to a relatively low positive voltage, typically varied in the positive range just above zero to V.sub.cc, preferably, +0.5 volts to +5.0 volts, and more preferably in the range +2.0 volts to +5.0 volts. Power supply voltage V.sub.cc is typically +5.0 volts. Drain 114 typically floats (High-Z). Source current may be relatively high, for example 20 to 30 milliamps for array 104, but is supplied at a voltage level less than or equal to the power supply voltage (e.g., V.sub.cc =+5 volts). Control gate current is suitably relatively small, e.g., 1 nanoamp or less per cell. As a result, the negative voltage on control gate 126 may be generated with a charge pump circuit integrated into the flash EEPROM.
While the source of the single supply EEPROM cells may be double-diffused (i.e. with deep well 130 and shallow well 132) as shown in FIG. 1, the lower source-to-substrate voltage during discharge for the cell permits the source to be single-diffused (i.e. no deep well 130) rather than double-diffused. Use of a single diffused source eliminates the initial diffusion step and subsequent thermal drive employed to create deep well 130, simplifying the process for fabricating the flash EEPROM. Further, while the values in Table I and the tunneling region 140 of FIG. 1 correspond to discharging floating gate 122 from the source, the source and drain connections during discharge could be switched, if desired, to effect discharge at the drain. This is particularly true when a single diffused source is employed.
Another type of known flash EEPROM employs a DIvided bit-line NOR (DINOR) architecture, which utilizes bulk charging and selective discharging of cells (as opposed to the selective charging and bulk discharging discussed above with reference to cells 110). The DINOR architecture is described in Koyabashi et al., "Memory Array Architecture and Decoding Scheme for 3 V Only Sector Erasable DINOR Flash Memory", IEEE Journal of Solid State Circuits, vol. 29, no. 4, Apr. 1994.
Briefly, however, referring to FIGS. 3 and 4, a DINOR flash EEPROM 500 typically comprises an array 504 of individual cells 510 and a control circuit 525. Each cell 510 typically comprises: single-diffused n-type source 5 12, p-type channel 518 and single-diffused n-type drain 514 regions formed in a P-well 550; and a selectively chargeable stacked gate structure 160 overlying channel 518 and a portion of source 512 and drain 514. DINOR flash EEPROM 500 is typically formed on a p-type substrate 516, with P-well 550 isolated from substrate 516 by a deep N-well 552. Deep N-well 552 suitably provides electrical isolation between array 504 and associated peripheral circuitry (not shown). Deep N-well 552 is typically grounded (FIG. 3), while P-well 550 is typically selectively connected to an external voltage source V.sub.SUB.
The cells 510 of array 504 are effectively grouped (i.e., array 504 is effectively divided) into a predetermined number of equal-sized sectors, each associated with a separate source line CS (and source driver circuitry). More specifically, the source of each cell in an individual sector is connected in common (typically formed as part of a common semiconductor region), but isolated from the sources of the cells of the other sectors. Each sector is, in turn, typically divided into respective upper and lower memory units, e.g. an upper bank 507 and lower bank 509 of cells 510. Each bank 507 and 509 is arranged in M rows (e.g. 8) and N columns (e.g. 512) for a total size of each sector within EEPROM 500 of N.times.M bits (e.g. 8K bits, or 1K byte).
Array 504 includes respective word lines (WL) and (main) bit lines (BL), generally corresponding to the word lines and bit lines of array 104 (FIGS. 1 and 2). However, each word line (WL) is associated with (e.g., incorporates the control gates of) a respective row of cells in each of upper memory bank 507 and lower memory bank 509. Likewise, each bit line is divided into respective alternative sub-bit lines SB-U and SB-L associated with corresponding columns of cells in upper memory unit 507 and lower memory unit 509, respectively. Bit line BL is selectively coupled to one or the other sub-bit lines SB-U and SB-L by a respective select transistor 511 and 5 13, suitably alternatively actuated by an upper select gate signal (USG) and an inverted lower select gate signal (LSG).
As previously noted, array 104 employs bulk discharge of cells 110, and selective charging of individual cells to effect the desired states (e.g. program the array). In contradistinction, DINOR array 504 employs bulk charging of cells, and selective discharge of cells to effect the desired cell states.
Charging of cells 510 within array 504 is typically effected in a different manner than cells 110. As discussed above, cells 110 are typically charged using hot electron injection, and bulk discharged via F-N tunneling. In DINOR array 504, both charging and discharging of cells 510 is typically performed via F-N tunneling. While charging by hot electron injection is substantially faster than charging via F-N tunneling, since the charging of cells 510 is done in bulk (all cells within a sector are charged concurrently), the consequence of the longer charging time of the F-N tunneling cycle is ameliorated.
Control circuit 525 may be any circuit suitable for selectively effecting connections to source (CS), control gate (WL), drain (BL) and P-well 550, to effect desired operations. Exemplary connections (conditions) for the various operating states of DINOR cells 510 are summarized in Table III.
TABLE III __________________________________________________________________________ V.sub.G (WL) V.sub.D (BL) Operation V.sub.S (CS) Selected Unselected Selected Unselected V.sub.SUB __________________________________________________________________________ Charge -8 +10 0 High-Z (Floating) -8 Read 0 +5 0 +1 to +2 0 0 Discharge High-Z (Floating) -8 0 +5 0 0 __________________________________________________________________________
In general, selective discharge of all of the bits in a given row is effected concurrently. Thus, the time required to discharge a cell is somewhat less critical than would be the case if the cells were discharged in seriatim; the effective discharge time is the time per cell for the F-N tunneling cycle divided by the number of cells in the row. For example, assuming that each word line has 512 bits, if the F-N cycle takes 100 milliseconds to perform, the effective write time per cell is 100 milliseconds/512, or approximately 200 microseconds per cell, which is comparable to the speed of individually programming (i.e. charging) cells 110 via hot electron injection. Each row, however, must be sequentially programmed. Thus, as the number of rows and sectors in EEPROM 500 increases, the amount of total time to discharge (program) the DINOR flash EEPROM device 500 becomes excessive. Therefore, there existed a need to improve the discharge time of prior art flash EEPROM devices, both for cells in a the standard flash EEPROM configuration, and in a DINOR arrangement.